Researchers at imec have unveiled a NAND-DRAM hybrid memory architecture based on charge-coupled device (CCD) technology, a development aimed at improving memory speed and cost efficiency. This innovative 3D CCD architecture addresses the “memory wall” bottleneck in AI computing, where processing units such as GPUs experience delays waiting for data due to inadequate memory bandwidth.
The design merges the speed and rewritability of DRAM with the density of NAND, distinguishing it from conventional flat memory cell arrangements by stacking memory cells vertically. This approach mimics 3D NAND architecture and offers potential benefits, including reduced leakage and improved cost efficiency due to the higher density of memory cells.
The CCD technology, traditionally used in digital cameras, has been adapted to enhance memory systems. imec’s prototype utilizes Indium Gallium Zinc Oxide (IGZO) instead of silicon, which promises advantages such as better data retention and lower power consumption. The prototype has achieved charge transfer speeds exceeding 4MHz, although it currently incorporates a limited number of stacked layers.
Imec projects that the 3D CCD architecture could scale similarly to NAND, with commercially available chips now exceeding 200 layers. The architecture is engineered for block-level data access, optimizing performance for modern AI workloads compared to byte-addressable DRAM. “Unlike byte-addressable DRAM, our 3D CCD device is designed to provide block-level data access, which is better suited to modern AI workloads,” said Maarten Rosmeulen, Program Director for Storage Memory.
Future plans position this architecture as a CXL Type-3 device, facilitating communication among GPUs, CPUs, and accelerators in line with industry standards. There are several challenges to address, including thermal management, layer scalability, and real-world integration of the prototype. However, if successful, this memory architecture could significantly reduce costs associated with DRAM in AI infrastructures.
Imec’s ongoing research may lead to the establishment of a new category of memory architectures that surpass current designs, indicating a promising future for memory technology advancements.
