IBM announced it has developed the world’s first sub-1 nanometer chip, utilizing its new “nanostack” architecture to create a functioning chip measuring 7 angstroms (0.7nm). This design achieves double the density of IBM’s previous 2nm chip, incorporating nearly 100 billion transistors within an area comparable to a human fingernail. The company claims this chip can deliver up to 50 percent more performance or 70 percent greater energy efficiency compared to its 2nm counterparts.
Jay Gambetta, director of IBM Research, stated the new architecture will enable significantly more powerful computing without a proportional increase in energy consumption. The “nanostack” design employs existing nanosheet transistor technology, allowing IBM to vertically stack and stagger the transistors. Each transistor comprises three nanosheet elements, approximately five nanometers thick, with about nine nanometers between them. Each nanosheet consists of 15 rows of silicon atoms.
IBM projects it will take approximately five years for nanostack chips to reach mass production. Rapidus, a Japanese chipmaker partnered with IBM, aims to begin producing 2nm chips at scale by the second half of 2027. IBM has indicated it will provide further details regarding its commercialization plans, emphasizing that its new technology paves the way for continued advancements in chip efficiency and power for at least the next decade.
