PCI-SIG has released the PCIe 8.0 specification with draft 0.5, detailing up to 1 TB/s bandwidth and 256 GT/s data rates. The standard is projected to be ready by 2028, targeting next-generation data centers.
PCIe 8.0 offers eight times the raw data rate and bandwidth of PCIe 5.0, providing 256 GT/s data rates and 1 TB/s bi-directional bandwidth through a 16x lane configuration. The specification employs PAM4 signaling technology and maintains backward compatibility with existing PCIe technology.
PCI-SIG announced that it is evaluating new connector technologies for use with PCIe 8.0. The group aims to enhance bandwidth through protocol improvements and reduce power consumption via new techniques. According to PCI-SIG, the development aligns with its long-term roadmap, which aims to double IO bandwidth every three years.
The breakdown of PCIe 8.0 bandwidth across various lane configurations includes: x1 offering 64 GB/s, x2 providing 128 GB/s, x4 yielding 256 GB/s, x8 delivering 512 GB/s, and x16 attaining 1024 GB/s. In x1 mode, PCIe 8.0 matches the bandwidth of PCIe 4.0 at x16 and PCIe 5.0 at x8 modes. At x2 mode, PCIe 8.0 achieves the full bandwidth of PCIe 5.0, while at x4 mode, it aligns with PCIe 6.0 capabilities.
PCI-SIG reported that draft 0.5 is available for member review ahead of schedule, reflecting member feedback from draft 0.3 released in September 2025. The primary objectives of PCIe 8.0 include supporting high bandwidth and low latency for data-intensive markets, such as artificial intelligence, data centers, high-speed networking, edge computing, and quantum computing.
