PCI-SIG announced it has released version 0.3 of the PCIe 8.0 specification to its members, detailing the objectives for the next-generation standard. The technology is being developed for future data-intensive workloads, including artificial intelligence, machine learning, high-speed networking, edge computing, and quantum computing. It is not intended for immediate consumer or gaming applications, as current PCIe 4.0 and PCIe 5.0 standards remain sufficient for those use cases.
The PCIe 8.0 specification is designed to deliver a raw bit rate of 256.0 GT/s and support up to 1.0 TB/s of bi-directional bandwidth in an x16 configuration. The standard will continue to use Pulse Amplitude Modulation 4-level (PAM4) signaling, a technology also implemented in the PCIe 6.0 and 7.0 specifications. The final version of the PCIe 8.0 specification is scheduled for completion by 2028.
Key development goals include achieving specific latency reductions and Forward Error Correction (FEC) performance. The group is also reviewing new connector technologies to accommodate higher speeds and confirming that reliability targets will be met. The specification will maintain backward compatibility with all previous PCIe generations. Additionally, development is focused on creating protocol enhancements to improve bandwidth efficiency and implementing techniques to reduce power consumption.
For comparison, current consumer-grade Gen4 SSDs offer speeds over 7 GB/sec, and Gen5 SSDs deliver more than 14 GB/sec. These speeds already exceed the requirements for typical gaming and general user tasks. The latest graphics cards do not fully saturate the bandwidth available on existing PCIe 5.0 slots.
