Intel’s latest 18A node is making waves in the semiconductor industry, outperforming competitors TSMC’s N2 and Samsung’s SF2 nodes in the 2nm performance class.
Intel’s 18A node achieved a performance score of 2.53, surpassing TSMC N2’s score of 2.27 and Samsung SF2’s score of 2.19. This positions Intel as a leader in the 2nm performance category. The superior performance of Intel 18A is attributed to its innovative features, including being the first node to incorporate a Backside Power Delivery Network (BSPDN).
The BSPDN significantly enhances the node’s performance by improving layout efficiency, component utilization, interconnect resistance, and ISO power performance. Specifically, BSPDN boosts layout efficiency and component utilization by 5-10%, lowers interconnect resistance, and enhances ISO power performance by up to 4%. This is achieved through a significant drop in intrinsic resistance compared to traditional front-end power routing.
In comparison to its predecessor, Intel 3, the 18A process delivers a 15% improvement in performance per watt and achieves a 30% increase in transistor density. These advancements underscore Intel’s progress in semiconductor technology, making its 18A node highly competitive.
Intel’s 18A node features the RibbonFET design, which has entered risk production. According to Intel, this stage involves stress-testing volume manufacturing before scaling up to high volume in the second half of 2025. This indicates that high-volume manufacturing is expected to follow shortly after, marking a significant milestone for the node.
The 18A node also showcases significant improvements in SRAM scaling. High-performance SRAM cells have shrunk to 0.023 µm², and high-density cells to 0.021 µm², demonstrating substantial scaling improvements. These advancements reflect scaling factors of 0.77 and 0.88, respectively, and challenge previous assumptions that SRAM scaling had plateaued.
Intel’s innovative “around-the-array” PowerVia approach further enhances the node’s capabilities. By routing power vias to I/O, control, and decoder circuits, this approach frees up the bit-cell area from frontal power supplies, resulting in a macro bit density of 38.1 Mbit/mm². This positions Intel to rival TSMC’s N2 node in terms of density.
The 18A node is set to feature in Panther Lake CPUs, which are slated for testing in late 2025 and shipments in early 2026. This upcoming deployment underscores the node’s readiness for integration into Intel’s next-generation processors, promising enhanced performance and efficiency for future computing applications.
